As integrated circuits for logic become even larger and more complex, usually as a result of further miniaturization of individual elements, it has become increasingly difficult to produce perfectly operating logic circuits at an acceptable yield. As the dimensions for the electrical components on the integrated circuit chip have become ever smaller, the processing margins have decreased. At an earlier date, the margins were sufficiently large that an acceptable yield of perfect, or good chips was more readily obtained. In addition, noise margins have been correspondingly decreasing. As a result a logic chip may operate satisfactorily a majority of the time but occasionally a noise transient is randomly impressed upon one of the internal lines and an incorrect operation results.
As a result, increasing attention has been devoted to error correcting logic, both for the hard failures of the exceeded processing margins and for the soft failures of the transient noise failures.
Also a large fraction of the failures are associated, not only with the logic functions themselves, but also with the interconnections between separated active devices. Internal logic signals often need to be conveyed relatively long distances. If there are a large number of such internal logic signal interconnections, the designer attempts to make the interconnection pathways as dense as possible. That is, the interconnections, typically of metal, are made very narrow and closely spaced. There are several failure modes for these interconnections. An interconnection can become separated somewhere in the middle so that the input to the following logic stage sees an open circuit, that is a floating potential. Another failure mode is that two neighboring, or adjacent, interconnections are shorted together. In many types of logic, when two wires carrying different signals are shorted together, one logic level will dominate over the other. Thus, in this failure mode in which one wire carries a high logic signal and the other carries a low logic signal, a short will produce a predetermined logic signal, for instance a high logic signal in many important technologies. A third failure mode is where the metal interconnection shorts to a fixed potential, forcing a false logic signal on a signal wire.